1. Field of the Invention
The present invention relates to a method of manufacturing a layered chip package that includes a plurality of semiconductor chips stacked.
2. Description of the Related Art
In recent years, a reduction in weight and an improvement in performance have been demanded of mobile devices typified by cellular phones and notebook personal computers. Accordingly, there has been a demand for higher integration of electronic components for use in mobile devices. Higher integration of electronic components has been demanded also for achieving an increase in capacity of semiconductor memory.
As an example of highly integrated electronic components, a system-in-package (hereinafter referred to as SiP), especially an SiP utilizing a three-dimensional packaging technology for stacking a plurality of semiconductor chips, has attracting attention in recent years. In the present application, a package that includes a plurality of semiconductor chips (hereinafter, also simply referred to as chips) stacked is called a layered chip package. Since the layered chip package allows a reduction in wiring length, it provides the advantage of allowing acceleration of the operation of circuits and a reduction in stray capacitance of wiring, as well as the advantage of allowing higher integration.
Major examples of the three-dimensional packaging technology for fabricating a layered chip package include a wire bonding method and a through electrode method. According to the wire bonding method, a plurality of chips are stacked on a substrate, and a plurality of electrodes formed on each chip are connected to external connecting terminals formed on the substrate by wire bonding. According to the through electrode method, a plurality of through electrodes are formed in each of the chips to be stacked and inter-chip wiring is performed through the use of the through electrodes.
The wire bonding method has the problem that it is difficult to reduce the distance between the electrodes so as to avoid contact between wires, and the problem that the high resistances of the wires hinder the acceleration of the operation of circuits.
The through electrode method is free from the above-mentioned problems of the wire bonding method. Unfortunately, however, the through electrode method requires a large number of steps for forming the through electrodes in chips, and consequently increases the cost for the layered chip package. According to the through electrode method, forming the through electrodes in chips requires a series of steps as follows: forming a plurality of holes for the plurality of through electrodes in a wafer that is to be cut later into a plurality of chips; forming an insulating layer and a seed layer in the plurality of holes and on the top surface of the wafer; forming a plurality of through electrodes by filling the plurality of holes with metal such as Cu by plating; and removing unwanted portions of the seed layer.
According to the through electrode method, the through electrodes are formed by filling metal into holes having relatively high aspect ratios. Consequently, voids or keyholes are prone to occur in the through electrodes due to poor filling of the holes with metal, so that the reliability of wiring formed by the through electrodes tends to be reduced.
According to the through electrode method, an upper chip and a lower chip are physically joined to each other by connecting the through electrodes of the upper and lower chips by means of, for example, soldering. The through electrode method therefore requires that the upper and lower chips be accurately aligned and then joined to each other at high temperatures. When the upper and lower chips are joined to each other at high temperatures, however, misalignment between the upper and lower chips can occur due to expansion and contraction of the chips, which often results in electrical connection failure between the upper and lower chips.
U.S. Pat. No. 5,953,588 discloses a method of manufacturing a layered chip package as described below. In this method, a plurality of chips cut out from a processed wafer are embedded into an embedding resin and then a plurality of leads are formed to be connected to each chip, whereby a structure called a neo-wafer is fabricated. Next, the neo-wafer is diced into a plurality of structures each called a neo-chip. Each neo-chip includes one or more chips, resin surrounding the chip(s), and a plurality of leads. The plurality of leads connected to each chip each have an end face exposed at a side surface of the neo-chip. Next, a plurality of types of neo-chips are laminated into a stack. In the stack, the respective end faces of the plurality of leads connected to the chips of each layer are exposed at the same side surface of the stack.
Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999, discloses the technique of fabricating a stack by the same method as that disclosed in U.S. Pat. No. 5,953,588, and forming wiring on two side surfaces of the stack.
Forming the wiring on the side surfaces of the stack as in the foregoing technique eliminates the problems associated with the wire bonding method and the through electrode method.
The manufacturing methods disclosed in U.S. Pat. No. 5,953,588 and in Keith D. Gann, “Neo-Stacking Technology”, HDI Magazine, December 1999 each involve a large number of process steps and this raises the cost for the layered chip package. According to the methods, a plurality of chips cut out from a processed wafer are embedded into the embedding resin, and then a plurality of leads are formed to be connected to each chip to thereby fabricate the neo-wafer. Accurate alignment between the plurality of chips is therefore required when fabricating the neo-wafer. This is also a factor that raises the cost for the layered chip package.
U.S. Pat. No. 7,127,807 B2 discloses a multilayer module formed by stacking a plurality of active layers each including a flexible polymer substrate with at least one electronic element and a plurality of electrically-conductive traces formed within the substrate. U.S. Pat. No. 7,127,807 B2 further discloses a manufacturing method for a multilayer module as described below. In the manufacturing method, a module array stack is fabricated by stacking a plurality of module arrays each of which includes a plurality of multilayer modules arranged in two orthogonal directions. The module array stack is then cut into a module stack which is a stack of a plurality of multilayer modules. Next, a plurality of conductive lines are formed on the respective side surfaces of the plurality of multilayer modules included in the module stack. The module stack is then separated into individual multilayer modules.
With the multilayer module disclosed in U.S. Pat. No. 7,127,807 B2, it is impossible to increase the proportion of the area occupied by the electronic element in each active layer, and consequently it is difficult to achieve higher integration.
To cope with this, as a method for manufacturing a layered chip package that achieves higher integration and has wiring formed on a side surface of the stack at low cost, the following manufacturing method is conceivable. In the manufacturing method, a plurality of wafers are initially fabricated, each of the wafers including an array of a plurality of pre-semiconductor-chip portions. Each of the pre-semiconductor-chip portions is intended to become a semiconductor chip. The plurality of wafers are then stacked into a wafer stack that includes an array of a plurality of pre-separation main bodies. The plurality of pre-separation main bodies are to be separated from each other later into individual main bodies of layered chip packages. The wafer stack is then cut into a structure that includes at least one portion to be the main body. Next, wiring is formed on the plurality of structures simultaneously.
In the foregoing manufacturing method, the plurality of structures may be aligned using a jig when forming the wiring. In this case, however, there arises the problem that differences in level can develop between the top surface of the jig and the top surfaces of the plurality of structures and between the top surfaces of adjoining structures, so that it is difficult to form the wiring with precision.